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| MC74VHCT00A Quad 2- Input NAND Gate The MC74VHCT00A is an advanced high speed CMOS 2-input NAND gate fabricated with silicon gate CMOS technology. It achieves high speed operation while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The device input is compatible with TTL-type input thresholds and the output has a full 5 V CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic-level translator from 3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high-voltage power supply. The MC74VHCT00A input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This allows the MC74VHCT00A to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when VCC = 0 V. These input and output structures help prevent device destruction caused by supply voltage - input/output voltage mismatch, battery backup, hot insertion, etc. http://onsemi.com MARKING DIAGRAMS 14 1 SOIC-14 D SUFFIX CASE 751A VHCT00A AWLYYWW 14 1 * * * * * * * * * * High Speed: tPD = 5.0 ns (Typ) at VCC = 5 V Low Power Dissipation: ICC = 2 A (Max) at TA = 25C TTL-Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 3.0 V to 5.5 V Operating Range Low Noise: VOLP = 0.8 V (Max) Pin and Function Compatible with Other Standard Logic Families Chip Complexity: 48 FETs or 12 Equivalent Gates These devices are available in Pb-free package(s). Specifications herein apply to both standard and Pb-free devices. Please see our website at www.onsemi.com for specific Pb-free orderable part numbers, or contact your local ON Semiconductor sales office or representative. 14 TSSOP-14 DT SUFFIX CASE 948G VHCT 00A AWLYWW 1 SOIC EIAJ-14 M SUFFIX CASE 965 VHCT00A ALYW A L, WL Y, YY W, WW = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device MC74VHCT00AD MC74VHCT00ADR2 MC74VHCT00ADT MC74VHCT00ADTEL MC74VHCT00ADTR2 MC74VHCT00AM MC74VHCT00AMEL Package SOIC--14 SOIC--14 TSSOP--14 Shipping 48 Units/Rail 2500 Units/Reel 96 Units/Rail TSSOP--14 2000 Units/Reel TSSOP--14 2000 Units/Reel SOIC EIAJ--14 SOIC EIAJ--14 48 Units/Rail 2000 Units/Reel (c) Semiconductor Components Industries, LLC, 2006 March, 2006 - Rev. 3 - 1 Publication Order Number: MC74VHCT00A/D MC74VHCT00A A1 VCC 14 B4 13 A4 12 Y4 11 B3 10 A3 9 Y3 8 B1 A2 B2 A3 B3 1 A1 2 B1 3 Y1 4 A2 5 B2 6 Y2 7 GND A4 B4 1 2 4 5 9 10 12 13 3 Y1 6 Y2 Y = AB 8 Y3 11 Y4 Figure 1. Pin Assignment (Top View) Figure 2. Logic Diagram FUNCTION TABLE PIN ASSIGNMENT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 IN A1 IN B1 OUT Y1 IN A2 IN B2 OUT Y2 GND OUT Y3 IN A3 IN B3 OUT Y4 IN A4 IN B4 VCC A1 B1 A2 B2 A3 B3 A4 B4 1 2 4 5 9 10 12 13 A L L H H Inputs B L H L H Output Y H H H L & 3 6 8 11 Y1 Y2 Y3 Y4 Figure 3. IEC LOGIC DIAGRAM http://onsemi.com 2 MC74VHCT00A MAXIMUM RATINGS (Note 1) Symbol VCC VIN VOUT IIK IOK IOUT ICC PD TL Tstg VESD DC Supply Voltage DC Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current, per Pin DC Supply Current, VCC and GND Power Dissipation in Still Air, SOIC Packages (Note 2) TSSOP Package (Note 2) VOUT < GND; VOUT > VCC VCC = 0 High or Low State Characteristics Value --0.5 to +7.0 --0.5 to +7.0 --0.5 to 7.0 --0.5 to VCC + 0.5 --20 +20 +25 +50 500 450 260 --65 to +150 Human Body Model (Note 3) Machine Model (Note 4) Charged Device Model (Note 5) Above VCC and Below GND at 125C > 2000 > 200 > 3000 300 Unit V V V mA mA mA mA mW C C V This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high--impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. Lead temperature, 1 mm from case for 10 s Storage temperature ESD Withstand Voltage ILatch--Up Latch--Up Performance (Note 6) mA * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute--maximum--rated conditions is not implied. 1. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute--maximum--rated conditions is not implied. Functional operation should be restricted to the Recommended Operating Conditions. 2. Derating -- SOIC Packages: -7 mW/_C from 65_ to 125_C -- TSSOP Package: --6.1 mW/_C from 65_ to 125_C 3. Tested to EIA/JESD22--A114--A 4. Tested to EIA/JESD22--A115--A 5. Tested to JESD22--C101--A 6. Tested to EIA/JESD78 RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN VOUT TA tr , tf DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature Range Input Rise and Fall Time VCC = 3.3 V 0.3 V VCC = 5.0 V 0.5 V VCC = 0 High or Low State Characteristics Min 3.0 0.0 0.0 0.0 --55 0 0 Max 5.5 5.5 5.5 VCC +125 100 20 Unit V V V C ns/V http://onsemi.com 3 MC74VHCT00A The JA of the package is equal to 1/Derating. Higher junction temperatures may affect the expected lifetime of the device per the table and figure below. DEVICE JUNCTION TEMPERATURE VERSUS TIME TO 0.1% BOND FAILURES Time, Hours 1,032,200 419,300 178,700 79,600 37,000 17,800 8,900 Time, Years 117.8 47.9 20.4 9.4 4.2 2.0 1.0 NORMALIZED FAILURE RATE Junction Temperature C 80 90 100 110 120 130 140 FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 130 C TJ = 120 C TJ = 110 C TJ = 100 C TJ = 80 C 100 TIME, YEARS TJ = 90 C 1 1 10 1000 Figure 4. Failure Rate vs. Time Junction Temperature DC ELECTRICAL CHARACTERISTICS VCC Symbol VIH Parameter Minimum High--Level Input Voltage Maximum Low--Level Input Voltage Minimum High--Level Output Voltage VIN = VIH or VIL VIN = VIH or VIL IOH = --50 A VIN = VIH or VIL IOH = --4 mA IOH = --8 mA VIN = VIH or VIL IOL = 50 A VIN = VIH or VIL IOL = 4 mA IOL = 8 mA VIN = 5.5 V or GND VIN = VCC or GND Input: VIN = 3.4 V VOUT = 5.5 V Test Conditions (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 3.0 4.5 3.0 4.5 3.0 4.5 0 to 5.5 5.5 5.5 0.0 2.9 4.4 2.58 3.94 0.0 0.0 0.1 0.1 0.36 0.36 0.1 2.0 1.35 0.5 3.0 4.5 Min 1.4 2.0 2.0 0.53 0.8 0.8 2.9 4.4 2.48 3.80 0.1 0.1 0.44 0.44 1.0 20 1.50 5.0 TA = 25C Typ Max TA 85C Min 1.4 2.0 2.0 0.53 0.8 0.8 2.9 4.4 2.34 3.66 0.1 0.1 0.52 0.52 1.0 40 1.65 10 Max TA 125C Min 1.4 2.0 2.0 0.53 0.8 0.8 Max Unit V VIL V VOH V V VOL Maximum Low--Level Output Voltage VIN = VIH or VIL V V IIN ICC ICCT IOPD Maximum Input Leakage Current Maximum Quiescent Supply Current Quiescent Supply Current Output Leakage Current A A mA A http://onsemi.com 4 MC74VHCT00A AC ELECTRICAL CHARACTERISTICS Cload = 50 pF, Input tr = tf = 3.0 ns TA = 25C Symbol tPLH, tPHL Parameter Maximum Propogation Delay, Input A or B to Y Test Conditions VCC = 3.3 0.3 V VCC = 5.0 0.5 V CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF Min Typ 4.1 5.5 3.1 3.6 5.5 Max 10.0 13.5 6.9 7.9 10 TA 85C Min Max 11.0 15.0 8.0 9.0 10 TA 125C Min Max 13.0 17.5 9.5 10.5 10 pF Unit ns CIN Maximum Input Capacitance Typical @ 25C, VCC = 5.0 V 17 CPD Power Dissipation Capacitance (Note 7) pF 7. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no--load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V, Measured in SO Package) TA = 25C Symbol VOLP VOLV VIHD VILD Characteristic Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Typ 0.4 -- 0.4 Max 0.8 -- 0.8 2.0 0.8 Unit V V V V TEST POINT A or B 3.0 V 50% tPLH Y 50% VCC tPHL VOH VOL *Includes all probe and jig capacitance GND DEVICE UNDER TEST OUTPUT CL* Figure 5. Switching Waveforms Figure 6. Test Circuit INPUT * OUTPUT *Parastic Diode Figure 7. Input Equivalent Circuit Figure 8. Output Equivalent Circuit http://onsemi.com 5 MC74VHCT00A PACKAGE DIMENSIONS D SUFFIX SOIC PACKAGE CASE 751A--03 ISSUE F --A14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. --B1 7 P 7 PL 0.25 (0.010) M B M G C R X 45 _ F --TSEATING PLANE D 14 PL 0.25 (0.010) M K TB S M A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 DT SUFFIX TSSOP PACKAGE CASE 948G--01 ISSUE O 14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE --W--. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 -----1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 -----0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ 0.10 (0.004) 0.15 (0.006) T U S M TU S V S N 2X L/2 14 8 0.25 (0.010) M L PIN 1 IDENT. 1 7 B --U- N F DETAIL E K K1 J J1 SECTION N-N --W- 0.15 (0.006) T U S A --V- C 0.10 (0.004) - - SEATING -TPLANE D G H DETAIL E http://onsemi.com 6 MC74VHCT00A M SUFFIX SOIC EIAJ PACKAGE CASE 965--01 ISSUE O NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX -----2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 -----1.42 INCHES MIN MAX -----0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 -----0.056 14 8 LE Q1 E HE M_ L DETAIL P 1 7 Z D e A VIEW P c b 0.13 (0.005) M A1 0.10 (0.004) ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800--282--9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082--1312 USA Phone: 480--829--7710 or 800--344--3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2--9--1 Kamimeguro, Meguro--ku, Tokyo, Japan 153--0051 Fax: 480--829--7709 or 800--344--3867 Toll Free USA/Canada Phone: 81--3--5773--3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 7 MC74VHCT00A/D |
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